Rapid development in both communication technology and computer technology has led to the requirement for higher speed circuits, more sensitive circuits and higher gain circuits. Such requirements have arisen at the same time as the further development of integrated circuit technology in which high packing densities in integrated circuits have become highly desirable.
Optical communication technology provides an illustrative example. Optical communication has been developing at a rapid rate during the last few years. High sensitivity in receivers is desirable because it increases the distance between repeaters and reduces the number of repeaters in a particular communication system. Also of importance in optical communication systems is high speed amplifiers which permit high bit rates to be transmitted. High speed amplifier systems are also of use in other types of circuits including logic circuits, memory circuits, analog switching, high-input-impedance amplifiers, integrated circuits, etc.
One of the most promising compound semiconductors for high speed, high gain devices is indium gallium arsenide and related compounds such as indium gallium arsenide phosphide. This is due to the high mobility and peak electron velocity exhibited by the III-V compound semiconductors. A particular difficulty is in fabricating suitable devices to take advantage of these properties. For example, the low barrier heights impose a limitation on the usefulness of Schottky barrier gates for MESFETS with indium gallium arsenide channel layers. Various corrective measures can be used to improve the barrier height characteristics, but a reliable process to produce such devices with reproducible characteristics has not been found.
A possible approach to this problem is to interpose a thin layer of insulator material or wide band-gap material between metal and channel layer to produce the required barrier height for the control gate. Attempts to use a thin layer of gallium arsenide as the barrier material resulted in unacceptably high reverse bias currents (see for example C. Y. Chen et al, IEEE Electron Device Letters, Vol. EDL-6, No. 1, January 1985.